/**
 @file ctc_register.h

 @author  Copyright (C) 2011 Centec Networks Inc.  All rights reserved.

 @date 2011-7-26

 @version v2.0

   This file contains all register related data structure, enum, macro and proto.
*/

#ifndef _CTC_REGISTER_H
#define _CTC_REGISTER_H
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "ctc_const.h"
#include "ctc_parser.h"
#include "ctc_register_frz.h"
#include "ctc_field.h"

/****************************************************************
*
* Defines and Macros
*
****************************************************************/

#define CTC_IP_HEADER_LEN               20
#define CTC_DUMP_DB_FILE_NAME     256
#define CTC_DUMP_DB_BIT_MAP_NUM     2
/**
 @brief  Define global chip capability type
*/
enum ctc_global_capability_type_e
{
    CTC_GLOBAL_CAPABILITY_LOGIC_PORT_NUM = 0,              /**< [GB.GG.D2.TM.TMM.AT] logic port num, include reserved logic port 0 to disable logic port */
    CTC_GLOBAL_CAPABILITY_MAX_FID,                                 /**< [GB.GG.D2.TM.TMM.TMA.AT] max fid */
    CTC_GLOBAL_CAPABILITY_MAX_VRFID,                            /**< [GB.GG.D2.TM.TMM.AT] max vrfid */
    CTC_GLOBAL_CAPABILITY_MAX_ACL_LOG_ID,                   /**< [TMM.AT] max acl random log id */
    CTC_GLOBAL_CAPABILITY_MAX_EACL_LOG_ID,                   /**< [TMM.AT] max egress acl random log id */
    CTC_GLOBAL_CAPABILITY_MCAST_GROUP_NUM,               /**< [GB.GG.D2.TM.TMM.AT] mcast group num, include l2mc, ipmc, vlan default entry, include reserved group id 0 for tx c2c packet on stacking  */
    CTC_GLOBAL_CAPABILITY_VLAN_NUM,                             /**< [GB.GG.D2.TM.TMM.TMA.AT] vlan num, include reserved vlan 0 */
    CTC_GLOBAL_CAPABILITY_VLAN_RANGE_GROUP_NUM,      /**< [GB.GG.D2.TM.TMM.AT] vlan range group num */
    CTC_GLOBAL_CAPABILITY_STP_INSTANCE_NUM,               /**< [GB.GG.D2.TM.TMM.TMA.AT] stp instance num */
    CTC_GLOBAL_CAPABILITY_LINKAGG_GROUP_NUM,          /**< [GB.GG.D2.TM.TMM.TMA.AT] linkagg group num */
    CTC_GLOBAL_CAPABILITY_LINKAGG_MEMBER_NUM,         /**< [GB.GG.D2.TM.TMM.TMA.AT] linkagg per group member num */
    CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_FLOW_NUM,       /**< [GB.GG.D2.TM.TMM.AT] linkagg dlb per group flow num */
    CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_MEMBER_NUM,     /**< [GB.GG.D2.TM.TMM.AT] linkagg per group dlb member num */
    CTC_GLOBAL_CAPABILITY_LINKAGG_DLB_GROUP_NUM,      /**< [GB.GG.D2.TM.TMM.AT] linkagg dlb group num */
    CTC_GLOBAL_CAPABILITY_ECMP_GROUP_NUM,                  /**< [GG.D2.TM.TMM.AT] ecmp group num, include reserved ecmp group id 0 to disable ecmp */
    CTC_GLOBAL_CAPABILITY_ECMP_MEMBER_NUM,               /**< [GB.GG.D2.TM.TMM.AT] ecmp per group member num */
    CTC_GLOBAL_CAPABILITY_ECMP_DLB_FLOW_NUM,            /**< [GG.D2.TM.TMM.AT] ecmp dlb flow num */
    CTC_GLOBAL_CAPABILITY_EXTERNAL_NEXTHOP_NUM,      /**< [GB.GG.D2.TM.TMM.AT] external nexthop num, include reserved nhid 0-2 refer to ctc_nh_reserved_nhid_t */
    CTC_GLOBAL_CAPABILITY_GLOBAL_DSNH_NUM,              /**< [GB.GG.D2.TM.TMM.AT] nexthop offset num, include reserved nexthop offset 0 for rspan */
    CTC_GLOBAL_CAPABILITY_MPLS_TUNNEL_NUM,                /**< [GB.GG.D2.TM.TMM.AT] mpls tunnel id num*/
    CTC_GLOBAL_CAPABILITY_ARP_ID_NUM,                          /**< [GB.GG.D2.TM.TMM.AT] max arp id num, include reserved arp id 0 to disable arp */
    CTC_GLOBAL_CAPABILITY_L3IF_NUM,                             /**< [GB.GG.D2.TM.TMM.AT] l3 interface num, include reserved ifid 0 to disable L3if */
    CTC_GLOBAL_CAPABILITY_OAM_SESSION_NUM,              /**< [GB.GG.D2.TM.TMM.AT] oam session num, include 1 reserved session */
    CTC_GLOBAL_CAPABILITY_NPM_SESSION_NUM,              /**< [GB.GG.D2.TM.TMM.AT] npm session num */
    CTC_GLOBAL_CAPABILITY_APS_GROUP_NUM,                 /**< [GB.GG.D2.TM.TMM.AT] aps group num */
    CTC_GLOBAL_CAPABILITY_TOTAL_POLICER_NUM,         /**< [GB.GG.D2.TM.TMM.AT] total policer num, include port, flow and service, include reserved policer id 0 to disable policer */
    CTC_GLOBAL_CAPABILITY_POLICER_NUM,                    /**< [GB.GG.D2.TM.TMM.AT] policer num, include flow and service, include reserved policer id 0 to disable policer */

    CTC_GLOBAL_CAPABILITY_TOTAL_STATS_NUM,              /**< [GB.GG.D2.TM.TMM.AT] total stats num, include reserved stats 0 to disable stats */
    CTC_GLOBAL_CAPABILITY_QUEUE_STATS_NUM,              /**< [GB.GG.D2.TM.TMM.AT] queue stats num */
    CTC_GLOBAL_CAPABILITY_POLICER_STATS_NUM,            /**< [GB.GG.D2.TM.TMM.AT] policer stats num */
    CTC_GLOBAL_CAPABILITY_SHARE1_STATS_NUM,             /**< [GG.D2.TM.TMM.AT] share1 stats num, include VRF,IPMC,MPLS VC label,TUNNEL Egress,SCL Egress,Nexthop,Nexthop MPLS PW,Nexthop Mcast,L3IF Egress,FID Ingress*/
    CTC_GLOBAL_CAPABILITY_SHARE2_STATS_NUM,             /**< [GG.D2.TM.TMM.AT] share2 stats num, include MPLS TUNNEL Label,TUNNEL Ingress,SCL Ingress,Nexthop MPLS LSP,L3IF Ingress,FID Egress */
    CTC_GLOBAL_CAPABILITY_SHARE3_STATS_NUM,             /**< [D2.TM.TMM.AT] global share3 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE4_STATS_NUM,             /**< [D2.TM.TMM.AT] global share4 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE5_STATS_NUM,             /**< [TMM.AT] global share5 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE6_STATS_NUM,             /**< [TMM.AT] global share6 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE7_STATS_NUM,             /**< [TMM.AT] global share7 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE8_STATS_NUM,             /**< [TMM.AT] global share8 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE9_STATS_NUM,             /**< [TMM.AT] global share9 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE10_STATS_NUM,            /**< [AT] global share10 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE11_STATS_NUM,            /**< [AT] global share11 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE12_STATS_NUM,            /**< [AT] global share12 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE13_STATS_NUM,            /**< [AT] global share13 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE14_STATS_NUM,            /**< [AT] global share14 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE15_STATS_NUM,            /**< [AT] global share15 stats num */
    CTC_GLOBAL_CAPABILITY_SHARE16_STATS_NUM,            /**< [AT] global share16 stats num */
    CTC_GLOBAL_CAPABILITY_ACL0_IGS_STATS_NUM,           /**< [GG.D2.TM.TMM.AT] acl0 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL1_IGS_STATS_NUM,           /**< [GG.D2.TM.TMM.AT] acl1 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL2_IGS_STATS_NUM,           /**< [GG.D2.TM.TMM.AT] acl2 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL3_IGS_STATS_NUM,           /**< [GG.D2.TM.TMM.AT] acl3 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL4_IGS_STATS_NUM,           /**< [TMM.AT] acl4 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL5_IGS_STATS_NUM,           /**< [TMM.AT] acl5 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL6_IGS_STATS_NUM,           /**< [TMM.AT] acl6 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL7_IGS_STATS_NUM,           /**< [TMM.AT] acl7 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL8_IGS_STATS_NUM,           /**< [TMM.AT] acl8 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL9_IGS_STATS_NUM,           /**< [TMM.AT] acl9 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL10_IGS_STATS_NUM,          /**< [TMM.AT] acl10 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL11_IGS_STATS_NUM,          /**< [TMM.AT] acl11 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL12_IGS_STATS_NUM,          /**< [TMM.AT] acl12 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL13_IGS_STATS_NUM,          /**< [TMM.AT] acl13 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL14_IGS_STATS_NUM,          /**< [TMM.AT] acl14 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL15_IGS_STATS_NUM,          /**< [TMM.AT] acl15 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL16_IGS_STATS_NUM,          /**< [AT] acl16 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL17_IGS_STATS_NUM,          /**< [AT] acl17 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL18_IGS_STATS_NUM,          /**< [AT] acl18 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL19_IGS_STATS_NUM,          /**< [AT] acl19 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL20_IGS_STATS_NUM,          /**< [AT] acl20 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL21_IGS_STATS_NUM,          /**< [AT] acl21 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL22_IGS_STATS_NUM,          /**< [AT] acl22 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL23_IGS_STATS_NUM,          /**< [AT] acl23 ingress stats num */
    CTC_GLOBAL_CAPABILITY_ACL0_EGS_STATS_NUM,           /**< [GG.D2.TM.TMM.AT] acl0 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL1_EGS_STATS_NUM,           /**< [TMM.AT] acl1 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL2_EGS_STATS_NUM,           /**< [TMM.AT] acl2 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL3_EGS_STATS_NUM,           /**< [TMM.AT] acl3 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL4_EGS_STATS_NUM,           /**< [AT] acl4 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL5_EGS_STATS_NUM,           /**< [AT] acl5 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL6_EGS_STATS_NUM,           /**< [AT] acl6 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL7_EGS_STATS_NUM,           /**< [AT] acl7 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL8_EGS_STATS_NUM,           /**< [AT] acl8 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL9_EGS_STATS_NUM,           /**< [AT] acl9 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL10_EGS_STATS_NUM,          /**< [AT] acl10 egress stats num */
    CTC_GLOBAL_CAPABILITY_ACL11_EGS_STATS_NUM,          /**< [AT] acl11 egress stats num */
    CTC_GLOBAL_CAPABILITY_ECMP_STATS_NUM,               /**< [GG.D2.TM.TMM.AT]  ecmp stats num */

    CTC_GLOBAL_CAPABILITY_ROUTE_MAC_ENTRY_NUM,        /**< [GB.GG.D2.TM.TMM.AT] route mac entry num */
    CTC_GLOBAL_CAPABILITY_MAC_ENTRY_NUM,                    /**< [GB.GG.D2.TM.TMM.AT] mac entry num, include l2mc */
    CTC_GLOBAL_CAPABILITY_BLACK_HOLE_ENTRY_NUM,        /**< [GB.GG.D2.TM.TMM.AT] black hole entry num */
    CTC_GLOBAL_CAPABILITY_HOST_ROUTE_ENTRY_NUM,       /**< [GG.D2.TM.TMM.AT] host route entry num */
    CTC_GLOBAL_CAPABILITY_LPM_ROUTE_ENTRY_NUM,         /**< [GG.D2.TM.TMM.AT] lpm route entry num */
    CTC_GLOBAL_CAPABILITY_IPMC_ENTRY_NUM,                  /**< [GG.D2.TM.TMM.AT] ipmc entry num */
    CTC_GLOBAL_CAPABILITY_MPLS_ENTRY_NUM,                  /**< [GB.GG.D2.TM.TMM.AT] mpls entry num*/
    CTC_GLOBAL_CAPABILITY_TUNNEL_ENTRY_NUM,              /**< [GG.D2.TM.TMM.AT] tunnel entry num */
    CTC_GLOBAL_CAPABILITY_L2PDU_L2HDR_PROTO_ENTRY_NUM,   /**< [GB.GG.D2.TM.TMM.AT] l2 pdu based l2 header protocol entry num */
    CTC_GLOBAL_CAPABILITY_L2PDU_MACDA_ENTRY_NUM,             /**< [GB.GG.D2.TM.TMM.AT] l2 pdu based macda entry num */
    CTC_GLOBAL_CAPABILITY_L2PDU_MACDA_LOW24_ENTRY_NUM, /**< [GB.GG.D2.TM.TMM.AT] l2 pdu based macda low 24bit entry num */
    CTC_GLOBAL_CAPABILITY_L2PDU_L2CP_MAX_ACTION_INDEX,    /**< [GB.GG.D2.TM.TMM.AT] l2 pdu l2cp max action index */
    CTC_GLOBAL_CAPABILITY_L3PDU_L3HDR_PROTO_ENTRY_NUM,   /**< [GB.GG.D2.TM.TMM.AT] l3 pdu based l3 header protocol entry num */
    CTC_GLOBAL_CAPABILITY_L3PDU_L4PORT_ENTRY_NUM,             /**< [GB.GG.D2.TM.TMM.AT] l3 pdu based l4 port entry num */
    CTC_GLOBAL_CAPABILITY_L3PDU_IPDA_ENTRY_NUM,                 /**< [GB.GG.D2.TM.TMM.AT] l3 pdu based ipda entry num */
    CTC_GLOBAL_CAPABILITY_L3PDU_MAX_ACTION_INDEX,              /**< [GB.GG.D2.TM.TMM.AT] l3 pdu max action index */
    CTC_GLOBAL_CAPABILITY_SCL_HASH_ENTRY_NUM,           /**< [GB.GG.D2.TM.TMM.AT] scl hash 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_SCL1_HASH_ENTRY_NUM,           /**< [TM.TMM.AT] scl hash 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_SCL_TCAM_ENTRY_NUM,           /**< [GB.GG.D2.TM.TMM.AT] scl tcam 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_SCL1_TCAM_ENTRY_NUM,      /**< [GB.GG.D2.TM.TMM.AT] scl tcam 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_SCL2_TCAM_ENTRY_NUM,      /**< [TM.TMM.AT] scl tcam 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_SCL3_TCAM_ENTRY_NUM,      /**< [TM.TMM.AT] scl tcam 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL_HASH_ENTRY_NUM,           /**< [GB.GG.D2.TM.TMM.AT] acl hash 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL0_IGS_TCAM_ENTRY_NUM,  /**< [GB.GG.D2.TM.TMM.AT] acl0 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL1_IGS_TCAM_ENTRY_NUM,  /**< [GB.GG.D2.TM.TMM.AT] acl1 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL2_IGS_TCAM_ENTRY_NUM,  /**< [GB.GG.D2.TM.TMM.AT] acl2 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL3_IGS_TCAM_ENTRY_NUM,  /**< [GB.GG.D2.TM.TMM.AT] acl3 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL4_IGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl4 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL5_IGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl5 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL6_IGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl6 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL7_IGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl7 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL8_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl8 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL9_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl9 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL10_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl10 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL11_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl11 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL12_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl12 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL13_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl13 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL14_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl14 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL15_IGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl15 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL16_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl16 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL17_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl17 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL18_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl18 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL19_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl19 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL20_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl20 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL21_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl21 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL22_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl22 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL23_IGS_TCAM_ENTRY_NUM,  /**< [AT] acl23 ingress 160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL0_EGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl0 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL1_EGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl1 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL2_EGS_TCAM_ENTRY_NUM,  /**< [D2.TM.TMM.AT] acl2 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL3_EGS_TCAM_ENTRY_NUM,  /**< [TMM.AT] acl3 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL4_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl4 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL5_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl5 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL6_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl6 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL7_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl7 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL8_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl8 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL9_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl9 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL10_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl10 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_ACL11_EGS_TCAM_ENTRY_NUM,  /**< [AT] acl11 egress  160bit key size entry num */
    CTC_GLOBAL_CAPABILITY_CID_PAIR_NUM,             /**< [D2.TM.TMM.AT] acl tcam cid entry num */
    CTC_GLOBAL_CAPABILITY_UDF_ENTRY_NUM,            /**< [D2.TM.TMM.AT] acl udf entry num */
    CTC_GLOBAL_CAPABILITY_DOT1AE_SC_NUM,            /**< [TMM] dot1ae sec chan num */
    CTC_GLOBAL_CAPABILITY_IPFIX_ENTRY_NUM,          /**< [GG.D2.TM.TMM.AT] ipfix entry num */
    CTC_GLOBAL_CAPABILITY_EFD_FLOW_ENTRY_NUM,       /**< [GG.D2.TM.TMM.AT] efd flow entry num */

    CTC_GLOBAL_CAPABILITY_MAX_LCHIP_NUM,            /**< [GB.GG.D2.TM.TMM.AT] max local chip num */
    CTC_GLOBAL_CAPABILITY_MAX_PHY_PORT_NUM,         /**< [GB.GG.D2.TM.TMM.AT] max phy port num */
    CTC_GLOBAL_CAPABILITY_MAX_PORT_NUM,             /**< [GB.GG.D2.TM.TMM.AT] max port num per chip */
    CTC_GLOBAL_CAPABILITY_MAX_CHIP_NUM,             /**< [GB.GG.D2.TM.TMM.AT] max gchip num */
    CTC_GLOBAL_CAPABILITY_PKT_HDR_LEN,              /**< [D2.TM.TMM.AT] the packet header length */

    CTC_GLOBAL_CAPABILITY_MAX
};
typedef enum ctc_global_capability_type_e ctc_global_capability_type_t;


/**
 @brief  Define ECMP dynamic type
*/
enum ctc_global_ecmp_dlb_mode_e
{
    CTC_GLOBAL_ECMP_DLB_MODE_ALL      = 1,         /**< [GG.D2.TM.TMM.AT] All flow do ECMP dynamic load balance. This is default mode */
    CTC_GLOBAL_ECMP_DLB_MODE_ELEPHANT = 2,    /**< [GG.D2.TM.TMM.AT] Only elephant(big) flow do ECMP dynamic load balance */
    CTC_GLOBAL_ECMP_DLB_MODE_TCP      = 3,        /**< [GG.D2.TM.TMM.AT] Only TCP flow do ECMP dynamic load balance */

    CTC_GLOBAL_ECMP_DLB_MODE_MAX
};
typedef enum ctc_global_ecmp_dlb_mode_e ctc_global_ecmp_dlb_mode_t;

/**
 @brief  Define ECMP dynamic rebalance type
*/
enum ctc_global_ecmp_rebalance_mode_e
{
    CTC_GLOBAL_ECMP_REBALANCE_MODE_NORMAL   = 1,    /**< [GG.D2.TM.TMM.AT] ECMP dynamic load balancing normal mode:if inactivity duration
                                                                                                       lapsed, use optimal member, else use assigned member.  This is default mode*/
    CTC_GLOBAL_ECMP_REBALANCE_MODE_FIRST    = 2,    /**< [GG.D2.TM.TMM.AT] ECMP dynamic load balancing first mode: only new flow
                                                                                                       use optimal member for the first time, than use assigned member */
    CTC_GLOBAL_ECMP_REBALANCE_MODE_PACKET   = 3,    /**< [GG.D2.TM.TMM.AT] ECMP dynamic load balancing packet mode: use optimal member every some(default is 256) packets */

    CTC_GLOBAL_ECMP_REBALANCE_MODE_MAX
};
typedef enum ctc_global_ecmp_rebalance_mode_e ctc_global_ecmp_rebalance_mode_t;

/**
 @brief  Define vlan range mode
*/
enum ctc_global_vlan_range_mode_e
{
    CTC_GLOBAL_VLAN_RANGE_MODE_SCL = 0,       /**< [GG.D2.TM.TMM] Vlan range only for scl. This is default mode */
    CTC_GLOBAL_VLAN_RANGE_MODE_ACL = 1,       /**< [GG.D2.TM.TMM] Vlan range only for acl */
    CTC_GLOBAL_VLAN_RANGE_MODE_SHARE = 2,     /**< [GG.D2.TM.TMM] Vlan range for scl and acl */

    CTC_GLOBAL_VLAN_RANGE_MODE_MAX
};
typedef enum ctc_global_vlan_range_mode_e ctc_global_vlan_range_mode_t;


enum ctc_global_igmp_snooping_mode_e
{
    CTC_GLOBAL_IGMP_SNOOPING_MODE_0 = 0,  /**< [D2.TM.TMM.AT] redirect igmp_snooping to cpu, default mode.
                                                    D2 can't do copp,TM can do copp. */
    CTC_GLOBAL_IGMP_SNOOPING_MODE_1 = 1,  /**< [D2.TM.TMM.AT] redirect igmp_snooping to cpu and user must config one COPP ACL entry based CTC_PKT_CPU_REASON_IGMP_SNOOPING*/
    CTC_GLOBAL_IGMP_SNOOPING_MODE_2 = 2,  /**< [GG.D2.TM.TMM.AT]copy igmp_snooping to cpu and do vlan flooding ,
                                                    can do copp at the same time ,[D2]:L3if must enable L2 bridge */
    CTC_GLOBAL_IGMP_SNOOPING_MODE_MAX
};
typedef enum ctc_global_igmp_snooping_mode_e ctc_global_igmp_snooping_mode_t;

struct ctc_global_flow_property_s
{
    uint8 igs_vlan_range_mode;            /**< [GG.D2.TM] Ingress vlan range mode, refer to ctc_global_vlan_range_mode_t */
    uint8 egs_vlan_range_mode;            /**< [GG.D2.TM.TMM] Egress vlan range mode, refer to ctc_global_vlan_range_mode_t */
};
typedef struct ctc_global_flow_property_s ctc_global_flow_property_t;

enum ctc_global_ipv6_addr_compress_mode_e
{
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_0 ,       /**< [D2.TM.TMM.TMA.AT] 127~64 
                                                      [TMA] 0-31*/
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_1 ,       /**< [D2.TM.TMM.TMA.AT] 123~60 
                                                      [TMA] 32-63 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_2 ,       /**< [D2.TM.TMM.TMA.AT] 119~56 
                                                      [TMA] 64-95 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_3 ,       /**< [D2.TM.TMM.TMA.AT] 115~52 
                                                      [TMA] 96-127 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_4 ,       /**< [D2.TM.TMM.AT] 111~48 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_5 ,       /**< [D2.TM.TMM.AT] 107~44 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_6 ,       /**< [D2.TM.TMM.AT] 103~40 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_7 ,       /**< [D2.TM.TMM.AT] 99~36 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_8 ,       /**< [D2.TM.TMM.AT] 95~32 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_9 ,       /**< [D2.TM.TMM.AT] 91~28 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_10 ,      /**< [D2.TM.TMM.AT] 87~24 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_11 ,      /**< [D2.TM.TMM.AT] 83~20 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_12 ,      /**< [D2.TM.TMM.AT] 79~16 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_13 ,      /**< [D2.TM.TMM.AT] 75~12 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_14 ,      /**< [D2.TM.TMM.AT] 71~8 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_15 ,      /**< [D2.TM.TMM.AT] 67~4 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_16 ,      /**< [D2.TM.TMM.AT] 63~0 */
    CTC_GLOBAL_IPV6_ADDR_COMPRESS_MODE_MAX
};
typedef enum ctc_global_ipv6_addr_compress_mode_e ctc_global_ipv6_addr_compress_mode_t;

enum ctc_global_acl_cid_mode_e
{
    CTC_GLOBAL_ACL_CID_MODE_SRC_DST,    /**<[TMM] ACL match 8 bit src cid and 8 bit dst cid */
    CTC_GLOBAL_ACL_CID_MODE_SRC,        /**<[TMM] ACL match 16 bit src cid */
    CTC_GLOBAL_ACL_CID_MODE_DST,        /**<[TMM] ACL match 16 bit dst cid */
    CTC_GLOBAL_ACL_CID_MODE_MAX = CTC_GLOBAL_ACL_CID_MODE_DST
};
typedef enum ctc_global_acl_cid_mode_e ctc_global_acl_cid_mode_t;

struct ctc_global_acl_property_s
{
    uint8  dir;                                 /**<[GG.D2.TM.TMM.AT]Direction,refer to ctc_direction_t*/
    /*Per ACL Lookup level (acl_priority) control*/
    uint8  lkup_level;                          /**<[GG.D2.TM.TMM.AT]ACL Lookup level*/
    uint8  discard_pkt_lkup_en;                 /**<[GG.D2.TM.TMM.AT] If set,indicate the discarded packets will do ACL lookup; For GG is not per level ctl,it is global ctl. */
    uint8  key_ipv6_da_addr_mode;               /**<[D2.TM.TMM.TMA.AT] for CTC_ACL_KEY_FWD/CTC_ACL_KEY_IPV6,ctc_global_ipv6_addr_compress_mode_t*/
    uint8  key_ipv6_sa_addr_mode;               /**<[D2.TM.TMM.TMA.AT] for CTC_ACL_KEY_FWD/CTC_ACL_KEY_IPV6 ctc_global_ipv6_addr_compress_mode_t*/
    uint8  key_cid_en;                          /**<[D2.TM.TMM] All Acl Key*/
    uint8  random_log_pri;                      /**<[D2.TM] Random log mapped new acl priority*/
    uint8  action_fid_en;                       /**<[TM.TMM.AT] if set, indicate action support fid*/
    uint8  stk_hdr_lkup_en;                     /**<[TMM] Stacking Header match acl*/
    uint8  key_cid_mode;                        /**<[TMM] Egress ACL key cid mode, refer to ctc_global_acl_cid_mode_t */
    uint8  key_stk_hdr_en;                      /**<[TMM] for CTC_ACL_KEY_MAC/CTC_ACL_KEY_MAC_IPV4 */
    uint8  npm_im_en;                           /**<[TMM] NPM In-Band Measurement Enable, it should not be paired with l2l3_key_u2_mode at the same time*/
    uint8  action_pri;                          /**<[TMM] The action priority of physical block, the physical block is specified by lkup_level field.
                                                                    0 means use default action priority, default action priority is reverse order of lkup_level*/
    uint8  l2l3_key_u2_mode;                    /**<[TMM.TMA] for CTC_ACL_KEY_MAC_IPV4, 0: ip hdr info ; 1: ip hdr ; 2: dst cid; 3: metadata,if set 3, npm_im_en is also be setted
                                                    [TMA] for CTC_ACL_KEY_MAC_EXT, 0: select sa as mac addr; 1: select da as mac addr */
    uint8  l2l3_key_u3_mode;                    /**<[TMM] for CTC_ACL_KEY_MAC_IPV4, 0: cpu reason; 1: from stacking port info, ip pkt len range and so on; 2: src cid; 3: metadata */
    uint8  eco_en;                              /**<[AT]  if set, the acl lookup level will be disable */

    /*global config*/
    uint8  copp_key_use_ext_mode[MAX_CTC_PARSER_L3_TYPE]; /**<[D2.TM.TMM.AT] default:CTC_PARSER_L3_TYPE_IPV6 use copp ext key;other use copp key*/
    uint8  l2l3_ext_key_use_l2l3_key[MAX_CTC_PARSER_L3_TYPE]; /**<[D2.TM.TMM.AT] default:CTC_PARSER_L3_TYPE_IP/CTC_PARSER_L3_TYPE_IPV4/CTC_PARSER_L3_TYPE_IPV6 use l2l3 ext key;other use l2l3 key*/
    uint8  l3_key_ipv6_use_compress_addr;       /**<[D2.TM.TMM.AT] if set,ipv6 address use compress mode (64 bit ipaddr),else ipv6 will use CTC_ACL_KEY_IPV6_EXT even if tcam lkup type is CTC_ACL_TCAM_LKUP_TYPE_L3*/
    uint8  cid_key_ipv6_da_addr_mode;           /**<[D2.TM.TMM.AT] for CTC_ACL_KEY_CID*/
    uint8  cid_key_ipv6_sa_addr_mode;           /**<[D2.TM.TMM.AT] for CTC_ACL_KEY_CID*/
    uint8  key_ctag_en;                         /**<[D2.TM.TMM.AT] default to STag,for CTC_ACL_KEY_INTERFACE/CTC_ACL_KEY_FWD/CTC_ACL_KEY_COPP/CTC_ACL_KEY_COPP_EXT.*/
    uint8  stp_blocked_pkt_lkup_en;             /**<[D2.TM.TMM.AT] If set, indicate the stp blocked packet will do ACL lookup.Only ingress valid */
    uint8  l2_type_as_vlan_num;                 /**<[GG.D2.TM.TMM.AT] if set,vlan number can be used as key rather than layer2 type*/
    uint8  fwd_ext_key_l2_hdr_en;               /**<[D2] If set, forward ext key will include layer2 header fields instead of udf fields */
    uint8  copp_key_use_udf;                    /**<[D2.TM] If set, copp key can match udf key */
    uint8  copp_ext_key_use_udf;                /**<[D2.TM] If set, copp ext key can match udf key */
    uint8  copp_key_fid_en;                     /**<[TM] If set, copp key and copp ext key can support CTC_FIELD_KEY_FID and  do not support CTC_FIELD_KEY_DST_NHID.
                                                         Else, this key do not support CTC_FIELD_KEY_FID and  support CTC_FIELD_KEY_DST_NHID again.*/
    uint8  fwd_key_fid_en;                      /**<[TM] If set, forward key and forward ext key can support CTC_FIELD_KEY_FID and  do not support CTC_FIELD_KEY_DST_NHID .
                                                         Else, this key do not support CTC_FIELD_KEY_FID and  support CTC_FIELD_KEY_DST_NHID again.*/
    uint8  l2l3_key_fid_en;                     /**<[TM] If set, macl3 ext key and macipv6 ext key can support CTC_FIELD_KEY_FID and  do not support CTC_FIELD_KEY_CVLAN_RANGE and CTC_FIELD_KEY_CTAG_COS.
                                                         Else, this key do not support CTC_FIELD_KEY_FID and  support CTC_FIELD_KEY_CVLAN_RANGE and CTC_FIELD_KEY_CTAG_COS again.*/
    uint8  key_use_arp_sender_mac;              /**<[TM.TMM.AT] If set, acl tcam key use sender mac as macsa when ArpPkt*/
    uint8  key_use_arp_target_mac;              /**<[TM.TMM.AT] If set, acl tcam key use target mac as macda when ArpPkt*/
    uint8  drop_reason_en;                      /**< [AT] If set, acl match drop reason, else match discard type */
    uint8  mac_ipv6_key_u0_mode;                /**<[TMM.TMA] for CTC_ACL_KEY_MAC_IPV6, 0: l2-type, ip-pkt-len-range and so on; 1: src-cid; 2: metadata 
                                                             [TMA] mac_ipv6 ipaddr1 64bit addr mode, 0: as ipv6 sa[63:0]  1: as ipv6 da[63:0]  */
    uint8  mac_ipv6_key_u1_mode;                /**<[TMM.TMA] for CTC_ACL_KEY_MAC_IPV6, 0: l4-type, interface-id; 1: dst-cid; 2: metadata
                                                              [TMA] mac_ipv6 ipaddr2 64bit addr mode, 0: as ipv6 sa[127:64]  1: as ipv6 da[127:64] */
    uint8  glb_acl_presel_en;                   /**<[TMM.AT] ACL presel mode, if set, use global presel, else use presel by lkup level, this feature not care direction */
    uint8  oam_pkt_lkup_disable;             /**<[D2.TM.TMM.AT] If set, ACL will not lookup packets from OAM engine */
};
typedef struct ctc_global_acl_property_s ctc_global_acl_property_t;

struct ctc_global_scl_property_s
{
    uint8  dir;                                 /**<[TMM.AT]Direction,refer to ctc_direction_t*/
    /*Per SCL Lookup level (scl_priority) control*/
    uint8  lkup_level;                          /**<[TMM.AT]SCL Lookup level*/
    uint8  ipv6_single_mode;                    /**<[TMM.AT]When enable CTC_PORT_IGS_SCL_TCAM_TYPE_IP_SINGLE on port, for ipv6 packet:
                                                       0: use 320 bits key, support 64bits ipda and 64bits ipsa, use CTC_SCL_KEY_TCAM_IPV6_SINGLE;
                                                       1: use 320 bits key, support ipsa, use CTC_SCL_KEY_TCAM_IPV6_SINGLE;
                                                       2: use 320 bits key, support ipda, use CTC_SCL_KEY_TCAM_IPV6_SINGLE;*/
    uint8  key_ipv6_da_addr_mode;               /**<[TMM.AT] for CTC_PORT_IGS_SCL_TCAM_TYPE_IP_SINGLE and ipv6_single_mode is 0, ctc_global_ipv6_addr_compress_mode_t*/
    uint8  key_ipv6_sa_addr_mode;               /**<[TMM.AT] for CTC_PORT_IGS_SCL_TCAM_TYPE_IP_SINGLE and ipv6_single_mode is 0, ctc_global_ipv6_addr_compress_mode_t*/
    uint8  key_ipv6_da_addr_len;                /**<[TMM.AT] for CTC_SCL_KEY_HASH_IPV6 of hash lookup mask*/
};
typedef struct ctc_global_scl_property_s ctc_global_scl_property_t;


enum ctc_global_presel_cid_e
{
    CTC_GLOBAL_PRESEL_PORT_CID   = 1U << 0,
    CTC_GLOBAL_PRESEL_VLAN_CID   = 1U << 1,
    CTC_GLOBAL_PRESEL_L3IF_CID   = 1U << 2,
    CTC_GLOBAL_PRESEL_SCL_CID    = 1U << 3,
    CTC_GLOBAL_PRESEL_TUNNEL_CID = 1U << 4,
    CTC_GLOBAL_PRESEL_FLOW_CID   = 1U << 5,
    CTC_GLOBAL_PRESEL_FID_CID    = 1U << 6,
    CTC_GLOBAL_PRESEL_NEXTHOP_CID= 1U << 7,
    CTC_GLOBAL_PRESEL_I2E_CID    = 1U << 8,
    CTC_GLOBAL_PRESEL_LDP_CID    = 1U << 9,
};
typedef enum ctc_global_presel_cid_e ctc_global_presel_cid_t;

struct ctc_global_cid_property_s
{
    uint32  global_cid;         /**<[D2.TM.TMM.AT] global src CID*/
    uint8   global_cid_en;      /**<[D2.TM.TMM.AT] enable global src CID */
    uint8   cid_pair_en;        /**<[D2.TM.TMM.AT] cid pair lookup enable */
    uint8   cmd_parser_en;      /**<[D2.TM.TMM.AT] cid metadata  parser enable*/
    uint8   cross_chip_cid_en;  /**<[D2.TM.TMM.AT] if set, stacking header will carry cid info*/
    uint16  cmd_ethtype;        /**<[D2.TM.TMM.AT]cid metadata  ethertype*/
    uint8   insert_cid_hdr_en;  /**<[D2.TM.TMM.AT]insert CID header*/
    uint8   reassign_cid_pri_en;   /**<[D2.TM.TMM.AT]re-assign CID priority*/
   /*direction*/
   uint8   is_dst_cid;          /**<[D2.TM.TMM.AT] if set,indicate cfg or get dst cid priority*/
   uint8   default_cid_pri;     /**<[D2.TM.TMM.AT] (src-cid|dst-cid) default CID Prioroty */
   uint8   fwd_table_cid_pri;   /**<[D2.TM.TMM.AT] (src-cid|dst-cid) forward table(ip/mac) CID Prioroty */
   uint8   flow_table_cid_pri;  /**<[D2.TM.TMM.AT] (src-cid|dst-cid) flow table(scl/sclflow) CID Prioroty */
   uint8   global_cid_pri;      /**<[D2.TM.TMM.AT] (src-cid) global CID Prioroty */
   uint8   pkt_cid_pri;         /**<[D2.TM.TMM.AT] (src-cid) packet's CID Prioroty */
   uint8   if_cid_pri;          /**<[D2.TM.TMM.AT] (src-cid) interface CID Prioroty */
   uint8   iloop_cid_pri;         /**<[D2.TM.TMM.AT] (src-cid) iloop header's CID Prioroty */

   uint16  presel_cid_bitmap;   /**<[TMM] Only support 4 presel cid bit set for ingress acl presel*/
   uint8   dir;                 /**<[AT] direction, refer to ctc_direction_t */
};
typedef struct ctc_global_cid_property_s ctc_global_cid_property_t;

struct ctc_global_ipmc_property_s
{
    uint8 ip_l2mc_mode;            /**< [D2.TM.TMM.TMA.AT] If set,ip base l2MC lookup failed,will use mac based L2MC lookup result.  */
    uint8 vrf_mode;                /**< [GG] If set, vrfid in IPMC key is svlan id.  */
};
typedef struct ctc_global_ipmc_property_s ctc_global_ipmc_property_t;

enum ctc_global_lag_dlb_mode_e
{
    CTC_LAG_DLB_MODE_PORT,         /**< [TMM.AT] Quality will be estimated depend on port load only*/
    CTC_LAG_DLB_MODE_QUEUE,        /**< [TMM.AT] Quality will be estimated depend on queue depth only*/
    CTC_LAG_DLB_MODE_PORT_QUEUE,   /**< [TMM.AT] Quality will be estimated depend on port load and queue depth together*/
    CTC_LAG_DLB_MODE_MAX
};
typedef enum ctc_global_lag_dlb_mode_e ctc_global_lag_dlb_mode_t;

struct ctc_global_lag_dlb_property_s
{
    uint32 interval;         /**< [D2.TM.TMM.AT] Time for lag dlb estimating quality, uint:us, 0 indicate invalid*/
    uint8 mode;              /**< [TMM.AT] Mode for lag dlb estimating quality, refer to ctc_global_lag_dlb_mode_t*/
    uint8 calc_type;         /**< [TMM.AT] If set, use EWMA(Exponentially Weighted Moving Average) to calculate average
                                        bandwidth and average queue depth,support all mode in ctc_global_lag_dlb_mode_t,
                                        else use DRE(Discounting Rate Estimator),only support CTC_LAG_DLB_MODE_PORT in ctc_global_lag_dlb_mode_t.
                                        In addition, only support DRE before TMM*/
    uint8 queue_percent;     /**< [TMM.AT] Percent of QueCount in determing quality, QueCount/(portLoad+QueCount),
                                        only for CTC_LAG_DLB_MODE_PORT_QUEUE in ctc_global_lag_dlb_mode_t*/
    uint8 port_weight;       /**< [D2.TM.TMM.AT] If calc_type set, mean lag dlb port load ewma weight<0-15> for calculating average bandwidth: 
                                        AvgPortLoading(t+1) = AvgPortLoading(t) + ((Portloading(t+1) - AvgPortLoading(t)) / 2 ^ weight),
                                        else,  mean lag dlb port load dre weight<0-15> for calculating average bandwidth:
                                        AvgPortLoading = AvgPortLoading * ( 1 - 1 / 2 ^ weight).*/
    uint8 queue_weight;      /**< [TMM.AT] Only valid when calc_type is set, mean lag dlb queue count ewma weight<0-15> for calculating average QueCount: 
                                        AvgQueCount(t+1) = AvgQueCount(t) + ((InstQueCount(t+1) - AvgQueCount(t)) / 2 ^ weight)*/
};
typedef struct ctc_global_lag_dlb_property_s ctc_global_lag_dlb_property_t;


struct ctc_global_panel_ports_s
{

    uint16  lport[CTC_MAX_PHY_PORT];       /**< [GB.GG.D2.TM.TMM.AT] all the valid ports */
    uint16   count;                                        /**< [GB.GG.D2.TM.TMM.AT] Port count num */
    uint8   lchip;                                          /**< [GB.GG.D2.TM.TMM.AT] Local device id     */
    uint8   rsv;
};
typedef struct ctc_global_panel_ports_s ctc_global_panel_ports_t;

struct ctc_global_dump_db_s
{
    uint32 bit_map[CTC_DUMP_DB_BIT_MAP_NUM];     /**< [D2.TM.TMM.AT] Bit map for dump module ctc_feature_t*/
    char   file[CTC_DUMP_DB_FILE_NAME];          /**< [D2.TM.TMM.AT] file of route and file name, NULL use default*/
    uint8  detail;                               /**< [D2.TM.TMM.AT] flag of dump detail data */
};
typedef struct ctc_global_dump_db_s ctc_global_dump_db_t;

enum ctc_global_macda_derive_mode_e
{
    CTC_GLOBAL_MACDA_DERIVE_FROM_NH,          /**< [TM.TMM.AT] macda all derive from nexthop */
    CTC_GLOBAL_MACDA_DERIVE_FROM_NH_ROUTE0,   /**< [TM.TMM.AT] macda low 2bits derive from route table, others derive from nexthop */
    CTC_GLOBAL_MACDA_DERIVE_FROM_NH_ROUTE1,   /**< [TM.TMM.AT] macda low 3bits derive from route table, others derive from nexthop */
    CTC_GLOBAL_MACDA_DERIVE_FROM_NH_ROUTE2,   /**< [TM.TMM.AT] macda low 4bits derive from route table, others derive from nexthop */

    CTC_GLOBAL_MAX_DERIVE_MODE
};
typedef enum ctc_global_macda_derive_mode_e ctc_global_macda_derive_mode_t;

struct ctc_global_overlay_decap_mode_e
{
    uint8 vxlan_mode;                     /**<[GG.D2.TM.TMM.AT] mode 0 decap by ipda + ipsa + vni, mode 1 decap by ipda + vni*/
    uint8 nvgre_mode;                     /**<[GG.D2.TM.TMM.AT] mode 0 decap by ipda + ipsa + vni, mode 1 decap by ipda + vni*/
    uint8 scl_id;                         /**<[GG.D2.TM.TMM.AT] scl id*/
};
typedef struct ctc_global_overlay_decap_mode_e ctc_global_overlay_decap_mode_t;

struct ctc_global_mem_chk_s
{
    uint32 mem_id;      /**< [TM.TMM.AT] [ in ] Ramid of memory check*/
    uint8  recover_en;  /**< [TM.TMM.AT] [ in ] If enable, recover the whole ram when compared result is wrong. */
    uint8  chk_fail;    /**< [TM.TMM.AT] [ out] Memory check fail*/
};
typedef struct ctc_global_mem_chk_s ctc_global_mem_chk_t;

enum ctc_register_xpipe_mode_s
{
    CTC_XPIPE_MODE_0,    /**< [TM.TMM.AT] Disable xpipe function */
    CTC_XPIPE_MODE_1,    /**< [TM.TMM.AT] Select high priority dest channel base on src channel */
    CTC_XPIPE_MODE_2,    /**< [TM.TMM.AT] Select high priority dest channel base on priority and color support two level*/
    CTC_XPIPE_MODE_3,    /**< [TMM.AT] Select high priority dest channel base on cut through packet*/
    CTC_XPIPE_MODE_4,    /**< [AT] Select high priority dest channel base on priority and color support three level*/
    CTC_XPIPE_MODE_5,    /**< [AT] Distinguish with source channel and priority + color */
    CTC_XPIPE_MODE_MAX,
};
typedef enum ctc_register_xpipe_mode_s ctc_register_xpipe_mode_t;

struct ctc_register_xpipe_action_s
{
    uint8 priority;    /**< [TM.TMM.AT] Priority value, used for xpipe key, range is 0-15 */
    uint8 color;       /**< [TM.TMM.AT] Color value, used for xpipe key, range is 0-3, 0 is all color, 1 is red, 2 is yellow, 3 is green*/
    uint8 is_high_pri;    /**< [TM.TMM.AT] Egress channel info, 1 go through high priority channel, 0 go throuth low priority channel
                            < [AT] Egress channel info, support three level, the value is 0-2, the higher the number, the higher the priority*/
};
typedef struct ctc_register_xpipe_action_s ctc_register_xpipe_action_t;

/* support key types of ctc_field_key_type_t:
 *********************************************************************************************************
 *              key                        |    desc      
 *--------------------------------------------------------------------------------------------------------
 *  l2 key  | CTC_FIELD_KEY_MAC_DA         |    ext_data:mac_addr_t, global config, only entry index 0 support
 *          | CTC_FIELD_KEY_MACDA_HIT      |    data:uint32, mean CTC_FIELD_KEY_MAC_DA is matched
 *          | CTC_FIELD_KEY_PKT_STAG_VALID |    data:uint32
 *          | CTC_FIELD_KEY_SVLAN_ID       |    data:uint32
 *          | CTC_FIELD_KEY_STAG_COS       |    data:uint32
 *          | CTC_FIELD_KEY_ETHER_TYPE     |    data:uint32
 *          | CTC_FIELD_KEY_PORT           |    data:unit32, mean config on the DP where the port is located
 *--------------------------------------------------------------------------------------------------------
 *  L3 key  | CTC_FIELD_KEY_IS_IP_PKT      |    data:uint32, ipv4/ipv6 packet and ipda is unicast.   
 *          | CTC_FIELD_KEY_IP_DSCP        |    data:uint32
 *--------------------------------------------------------------------------------------------------------
 *  L4 key  | CTC_FIELD_KEY_IP_PROTOCOL    |    data:uint32
 *          | CTC_FIELD_KEY_UDF            |    data:uint32, L4 data, ip pkt: start after ip header
            |                              |                      non-ip pkt: start after ether type
 *********************************************************************************************************/
struct ctc_register_xpipe_classify_s
{
   uint8  index;                  /**< [TMM.AT] Entry index<0-3>*/
   uint8  valid;                  /**< [TMM.AT] Control the entry is valid or not.*/
   uint8  obm_priority;           /**< [AT] OBM priority<0-3>, Per Datapath id config, valid when field_list have CTC_FIELD_KEY_PORT*/
   uint8  field_cnt;              /**< [TMM.AT] Key Field count */
   ctc_field_key_t  *field_list;  /**< [TMM.AT] Key Field list */
};
typedef struct ctc_register_xpipe_classify_s ctc_register_xpipe_classify_t;
struct ctc_global_flow_recorder_e
{
    uint8 queue_drop_stats_en;         /**< [TM] Enable statistics on discarded packet for queue congestion*/
    uint8 resolve_conflict_en;         /**< [TM] Enable resolve hash conflict*/
    uint8 resolve_conflict_level;      /**< [TM] Acl priority for resolve hash conflict*/
};
typedef struct ctc_global_flow_recorder_e ctc_global_flow_recorder_t;

struct ctc_global_hmac_s
{
    uint8 enable;                                   /**< [TMM] Enable HMAC */
    uint8 ip_protocol_en;                           /**< [TMM] HMAC use specified protocol */
    uint8 ip_protocol;                              /**< [TMM] Specified protocol value */
    uint8 ip_header_mask[CTC_IP_HEADER_LEN];        /**< [TMM] IP Header Mask */
};
typedef struct ctc_global_hmac_s ctc_global_hmac_t;

struct ctc_global_martian_addr_s
{
    uint8 index;                                    /**< [TMM.AT] Index of martian address, IPv4 support 2 address, IPv6 support 1 address */
    uint8 ip_ver;                                   /**< [TMM.AT] IP version, refers to ctc_ip_ver_t */
    uint8 masklen;                                  /**< [TMM.AT] Masklen for ip address */
    union
    {
        ip_addr_t ipv4;                             /**< [TMM.AT]IPv4 address */
        ipv6_addr_t ipv6;                           /**< [TMM.AT]IPv6 address */
    } addr;
};
typedef struct ctc_global_martian_addr_s ctc_global_martian_addr_t;

/**
 @brief Define SDK init module type, default init_flag value is CTC_INIT_MODULE_FCOE-1
*/
enum ctc_global_eco_mode_e
{
    CTC_GLOBAL_ECO_MCU           = 1U << 0,          /**< [TMM.AT] if set, the function of mcu will be disable */
    CTC_GLOBAL_ECO_MDIO          = 1U << 1,          /**< [TMM.AT] if set, the function of mdio will be disable */
    CTC_GLOBAL_ECO_OOBFC         = 1U << 2,          /**< [TMM] if set, the function of oobfc will be disable */
    CTC_GLOBAL_ECO_LED           = 1U << 3,          /**< [TMM.AT] if set, the function of led will be disable */
    CTC_GLOBAL_ECO_I2C           = 1U << 4,          /**< [AT] if set, the function of i2c will be disable */
    CTC_GLOBAL_ECO_GPIO          = 1U << 5,          /**< [AT] if set, the function of gpio will be disable */
    CTC_GLOBAL_ECO_HIBERNATE     = 1U << 6,          /**< [TMM.AT] if set, the chip all function will be disable */
    CTC_GLOBAL_ECO_MAX           = 1U << 7
};
typedef enum ctc_global_eco_mode_e ctc_global_eco_mode_t;

struct ctc_global_vchip_info_s
{
    uint8 pp_base;
    uint8 pp_num;
};
typedef struct ctc_global_vchip_info_s ctc_global_vchip_info_t;

struct ctc_truncation_len_s
{
    uint8  profile_id;           /**< [D2.TM.TMM.AT] Set truncation profile_id*/
    uint16 truncated_len;        /**< [D2.TM.TMM.AT] The length of packet after truncate, value 0 is disable*/
};
typedef struct ctc_truncation_len_s ctc_truncation_len_t;

enum ctc_truncation_mode_e
{
    CTC_TRUNCATION_MODE_0,           /**< truncation-en and truncation length based on flow */
    CTC_TRUNCATION_MODE_1,           /**< truncation-en based on port, truncation length based on global config*/
    CTC_TRUNCATION_MODE_2,           /**< truncation-en based on port and flow, truncation length based on global config*/
    CTC_TRUNCATION_MODE_MAX
};
typedef enum ctc_truncation_mode_e ctc_truncation_mode_t;

/**
 @brief Define SDK npm im mode
*/
enum ctc_global_npm_im_flag_e
{
    CTC_GLOBAL_NPM_IM_NONE       = 0,               /**< [TM.TMM] defult, disable all im function */
    CTC_GLOBAL_NPM_IM_MPLS       = 1U << 0,         /**< [TMM] if set, support mpls im function */
    CTC_GLOBAL_NPM_IM_IP_ECN     = 1U << 1,         /**< [TM.TMM] if set, support im with ip ecn field */
    CTC_GLOBAL_NPM_IM_MAX        = 1U << 2,
};
typedef enum ctc_global_npm_im_flag_e ctc_global_npm_im_flag_t;

/**
 @brief  global control type
*/
enum ctc_global_control_type_e
{
    CTC_GLOBAL_DISCARD_SAME_MACDASA_PKT = 0,   /**< [GB.GG.D2.TM.TMM.AT]value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_SAME_IPDASA_PKT,            /**< [GB.GG.D2.TM.TMM.AT]value: bool*, TRUE or FALSE */

    CTC_GLOBAL_DISCARD_TTL_0_PKT,                         /**< [GB.GG.D2.TM.TMM.AT]value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_MCAST_SA_PKT,                  /**< [GB.GG.D2.TM.TMM.AT.TMA] MAC SA is mcast address, value: bool*, TRUE or FALSE */

    CTC_GLOBAL_DISCARD_TCP_SYN_0_PKT,                 /**< [GB.GG.D2.TM.TMM.AT] TCP packets with SYN equals 0, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_TCP_FRAG_OFFSET_1_PKT,         /**< [TM.TMM.AT] TCP packet with fragment offset 1 will be droped, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_TCP_NULL_PKT,                   /**< [GB.GG.D2.TM.TMM.AT] TCP packets with flags and sequence number equal 0, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_TCP_XMAS_PKT,                  /**< [GB.GG.D2.TM.TMM.AT] TCP packets with FIN, URG, PSH bits set and sequence number equals 0, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_TCP_SYN_FIN_PKT,              /**< [GB.GG.D2.TM.TMM.AT] TCP packets with SYN & FIN bits set, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_SAME_L4_PORT_PKT,           /**< [GB.GG.D2.TM.TMM.AT] Same L4 source and destination port packets, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_ICMP_FRAG_PKT,             /**< [GB.GG.D2.TM.TMM.AT] Fragmented ICMP packets, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_DISCARD_IP_MARTIAN_ADDR_PKT,     /**< [TMM.AT] Set self define IP martian address */

    CTC_GLOBAL_ARP_MACDA_CHECK_EN,                 /**< [GB.GG.D2.TM.TMM.AT] Drop ARP reply packets which macda not equal to target mac, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_ARP_MACSA_CHECK_EN,                 /**< [GB.GG.D2.TM.TMM.AT] Drop ARP packets which macsa not equal to sender mac, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_ARP_IP_CHECK_EN,                   /**< [GB.GG.D2.TM.TMM.AT] Drop ARP packets with invalid sender ip or ARP reply packets with invalid target ip(0x0/0xFFFFFFFF/Mcast)value: bool*, TRUE or FALSE */
    CTC_GLOBAL_ARP_CHECK_FAIL_TO_CPU,             /**< [GB.GG.D2.TM.TMM.AT] ARP packets check fail and copy to cpu, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_GRATUITOUS_ARP_TO_CPU,             /**< [TMM.AT] Gratuitous ARP packets will be copied to cpu, value: bool*, TRUE or FALSE, default is TRUE */
    CTC_GLOBAL_ARP_LOCAL_CHECK_EN,                /**< [TMM.AT] ARP packets which to local will be copied to cpu, value: bool*, TRUE or FALSE, default is FALSE */

    CTC_GLOBAL_IGMP_SNOOPING_MODE,                /**< [D2.TM.TMM.AT]  enhanced IGMP Snooping,  value : refer to ctc_global_igmp_snooping_mode_t  */

    CTC_GLOBAL_ACL_CHANGE_COS_ONLY,                  /**< [GG]acl vlan edit actioin only change cos, value: bool*, TRUE or FALSE */

    CTC_GLOBAL_ECMP_DLB_MODE,                             /**< [GG.D2.TM.TMM.AT] ecmp dynamic load balancing mode, value uint32* refer to ctc_global_ecmp_dlb_mode_t */
    CTC_GLOBAL_ECMP_REBALANCE_MODE,                  /**< [GG.D2.TM.TMM.AT] ecmp dlb rebalance mode, value uint32* refer to ctc_global_ecmp_rebalance_mode_t */
    CTC_GLOBAL_ECMP_FLOW_AGING_INTERVAL,          /**< [GG.D2.TM.TMM.AT] ecmp dlb flow aging time, uint:ms, value uint32*, 0:disable flow aging */
    CTC_GLOBAL_ECMP_FLOW_INACTIVE_INTERVAL,      /**< [GG.D2.TM.TMM.AT] used for CTC_GLOBAL_ECMP_REBALANCE_MODE_NORMAL dynamic mode, ecmp dlb flow inactive time,0 indicate inactive immediately, uint:us, value uint32* */
    CTC_GLOBAL_ECMP_FLOW_PKT_INTERVAL,               /**< [GG.D2.TM.TMM.AT] used for CTC_GLOBAL_ECMP_REBALANCE_MODE_PACKET dynamic mode, select optimal member every 256/1024/8192/32768 packets, value uint32* */

    CTC_GLOBAL_LINKAGG_FLOW_INACTIVE_INTERVAL,        /**< [GB.GG.D2.TM.TMM.AT] used for Linkagg DLB mode, flow inactive time, uint:ms, value uint32* */
    CTC_GLOBAL_SPM_AGING_INTERVAL,                    /**< [TMM.AT] used for set session preservation flow aging timer interval */
    CTC_GLOBAL_STACKING_TRUNK_FLOW_INACTIVE_INTERVAL, /**< [GB.GG.D2.TM.TMM.AT] used for Stacking trunk DLB mode, flow inactive time, uint:ms, value uint32* */
    CTC_GLOBAL_LAG_DLB_PROPERTY,                      /**< [TMM.AT] Cfg global lag dlb property, refer to ctc_global_lag_dlb_property_t */

    CTC_GLOBAL_WARMBOOT_STATUS,                          /**< [GG.D2.TM.TMM.AT] warmboot status */
    CTC_GLOBAL_WARMBOOT_CPU_RX_EN,                   /**< [GG.D2.TM.TMM.AT] warmboot cpu rx enable, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_FLOW_PROPERTY,                               /**< [GG.D2.TM.TMM] Flow property, value:ctc_global_flow_property_t* */
    CTC_GLOBAL_CHIP_CAPABILITY,                              /**< [GB.GG.D2.TM.TMM.TMA.AT] Chip capability, value: uint32 chip_capability[CTC_GLOBAL_CAPABILITY_MAX], capability invalid value 0xFFFFFFFF means not support */
    CTC_GLOBAL_ACL_PROPERTY,                            /**< [GG.D2.TM.TMM.TMA.AT] Cfg global acl property, refer to ctc_global_acl_property_t */
    CTC_GLOBAL_SCL_PROPERTY,                            /**< [GG.D2.TM.TMM.AT] Cfg global scl property, refer to ctc_global_scl_property_t */
    CTC_GLOBAL_CID_PROPERTY,                            /**< [D2.TM.TMM.AT] Cfg global cid property, refer to ctc_global_cid_property_t */
    CTC_GLOBAL_ACL_LKUP_PROPERTY,                       /**< [D2.TM.TMM.AT] Cfg global acl lookup property, refer to ctc_acl_property_t */
    CTC_GLOBAL_ELOOP_USE_LOGIC_DESTPORT,                /**< [GG.D2.TM.TMM.AT] Eloop use logic dest port instand of logic src port, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_PIM_SNOOPING_MODE,                       /**< [GB.GG.D2.TM.TMM.AT] PIM snooping mode, mode 0: (GB/GG)PIM snooping recognized as IGMP snooping and per vlan/l3if enable; mode 1:PIM snooping recognized by acl, value uint32* */
    CTC_GLOBAL_IPMC_PROPERTY,                           /**< [GG.D2.TM.TMM.TMA.AT] Cfg global ipmc property, refer to ctc_global_ipmc_property_t */
    CTC_GLOBAL_VXLAN_UDP_DEST_PORT,                     /**< [GG.D2.TM.TMM.AT] vxlan protocol udp dest port, value: uint32, default is 4789 */
    CTC_GLOBAL_GENEVE_UDP_DEST_PORT,                    /**< [GG.D2.TM.TMM.AT] geneve protocol udp dest port, value: uint32, default is 6081 */
    CTC_GLOBAL_PANEL_PORTS,                             /**< [GB.GG.D2.TM.TMM.AT] get all panel ports in the chip */
    CTC_GLOBAL_NH_FORCE_BRIDGE_DISABLE,                 /**< [GB.GG.D2.TM.TMM.AT] Disable force bridge function for IPMC when src l3if match dest l3if, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_NH_MCAST_LOGIC_REP_EN,                   /**< [GB.GG.D2.TM] Enable nexthop mcast logic replication, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_LB_HASH_KEY,                             /**< [TM.TMM] load banlance hash key select and control value: void* refer to ctc_lb_hash_config_t, substitute by ctcs_parser_set_lb_hash_field*/
    CTC_GLOBAL_LB_HASH_OFFSET_PROFILE,                  /**< [TM.TMM] load banlance hash offset profile value: void* refer to ctc_lb_hash_offset_s, substitute by ctcs_parser_set_lb_hash_offset*/
    CTC_GLOBAL_VPWS_SNOOPING_PARSER,                    /**< [TM.TMM.AT] Enable parser VPWS payload */
    CTC_GLOBAL_VXLAN_CRYPT_UDP_DEST_PORT,               /**< [TM.TMM.AT] vxlan UDP dest port in cloudSec scenario, value: uint32, default is 0 */
    CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_UDP_DEST_PORT,        /**< [AT] UDP dest port in ctcSec shim, value: uint32, default is 0 */
    CTC_GLOBAL_DOT1AE_CRYPT_IP_PROTOCOL,                /**< [AT] Ip protocol in CTCSEC, value: uint8, default is 0xFE */
    CTC_GLOBAL_DOT1AE_CRYPT_CTCSH_IP_PROTOCOL,          /**< [AT] Ip protocol in CTCSEC with centec security header, value: uint8, default is 0xFD */
    CTC_GLOBAL_OAM_POLICER_EN,                          /**< [D2.TM.TMM.AT] Enable oam flow policer, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_PARSER_OUTER_ALWAYS_CVLAN_EN,            /**< [D2.TM.TMM.AT] Enable outer vlan is always cvlan when port is cvlan-domain, value: bool*, TRUE or FALSE */
    CTC_GLOBAL_NH_ARP_MACDA_DERIVE_MODE,                /**< [TM.TMM.AT] Config host route nexthop macda derive mode, refer to ctc_global_macda_derive_mode_t*/
    CTC_GLOBAL_ARP_VLAN_CLASS_EN,                       /**< [GG.D2.TM.TMM.AT] Enable ARP PDUS vlan classification */

    CTC_GLOBAL_DISCARD_MACSA_0_PKT,                     /**< [D2.TM.TMM.AT.TMA] Discard the packet that macSa is all zero, value: bool*, TRUE or FALSE*/
    CTC_GLOBAL_TPOAM_VPWSOAM_COEXIST,                   /**< [D2] If set, vpws oam and tp oam can coexit, and vpws oamid only support 0~2K; Else, vpws oam and tp oam can not coexist*/
    CTC_GLOBAL_VXLAN_POLICER_GROUP_ID_BASE,             /**< [TM] vxlan policer group id base, if set, group id value should be base~base+255 */
    CTC_GLOBAL_INBAND_CPU_TRAFFIC_TIMER,                /**< [D2.TM.TMM.AT] Set inband CPU traffic timer, 0 means disable, valid range 10(ms) ~100(ms). Only used for WDM Pon*/
    CTC_GLOBAL_DUMP_DB,                                 /**< [D2.TM.TMM.AT] Dump module master db to file*/
    CTC_GLOBAL_IGS_RANDOM_LOG_SHIFT,                    /**< [GG.D2.TM.TMM.AT] ingress port random log shift */
    CTC_GLOBAL_EGS_RANDOM_LOG_SHIFT,                    /**< [GG.D2.TM.TMM.AT] egress port random log shift */
    CTC_GLOBAL_OVERLAY_DECAP_MODE,                      /**< [GG.D2.TM.TMM.AT] overlay decap mode, refer to ctc_global_overlay_decap_mode_t*/
    CTC_GLOBAL_EGS_STK_ACL_DIS,                         /**< [GG.D2.TM.TMM.AT] Disable acl lookup in statkcing port's egress direction*/
    CTC_GLOBAL_STK_WITH_IGS_PKT_HDR_EN,                 /**< [D2.TM.TMM.AT] Enable or disable to remote cpu in stacking, within ingress chip packet header.  value: bool, default is FALSE*/
    CTC_GLOBAL_NET_RX_EN,                               /**< [TM] Net rx enable/disable*/
    CTC_GLOBAL_MEM_CHK,                                 /**< [TM.TMM.AT] Enable memory check, compare chip hardware data with the sofeware backup data*/
    CTC_GLOBAL_WARMBOOT_INTERVAL,                       /**< [TM.TMM.AT] Warmboot direct memory mode, sync timer interval config, uint:ms, value uint32* */
    CTC_GLOBAL_FDB_SEARCH_DEPTH,                        /**< [TM.TMM.AT] The max search depth for fdb hash reorder algorithm*/
    CTC_GLOBAL_EACL_SWITCH_ID,                          /**< [TM] used for egress acl action switch id, value: 0xFFFF(disable)*/
    CTC_GLOBAL_FLOW_RECORDER_EN,                        /**< [TM] Config flow recorder, refer to ctc_global_flow_recorder_t*/
    CTC_GLOBAL_XPIPE_MODE,                              /**< [TM] Xpipe mode, refers to ctc_register_xpipe_mode_s */
    CTC_GLOBAL_XPIPE_ACTION,                            /**< [TM.TMM.AT] Used in mode 2, distinguish packets with prio + color, refers to ctc_register_xpipe_action_t */
    CTC_GLOBAL_XPIPE_CLASSIFY,                          /**< [TMM.AT] Distinguish packets with packet fields, refers to ctc_register_xpipe_classify_t */
    CTC_GLOBAL_HMAC_EN,                                 /**< [TMM] Enable HMAC, refer to ctc_global_hmac_t */
    CTC_GLOBAL_ESLB_EN,                                 /**< [TM.TMM.AT] Enable EsLabel, value: uint32* */
    CTC_GLOBAL_NPM_IM_EN,                               /**< [TM.TMM] Enable NPM In-Band Measurement, uint32*, refer to ctc_global_npm_im_flag_t*/
    CTC_GLOBAL_NPM_IM_LOSS_PROF_INTERVAL,               /**< [TMM] Loss measurement invterval, and 0 means disable, uint:1s */
    CTC_GLOBAL_L2_RMAC_MATCH_EN,                        /**< [TMM.AT] Enable Router Mac match by L2 */
    CTC_GLOBAL_SID_EDIT_MODE,                           /**< [TMM.AT] For SRv6, value: uint32*  0: ipda is from srh, support 3 SIDs; 1: ipda is from srv6 nexthop, support 4 SIDs, always reduce mode*/
    CTC_GLOBAL_FORCE_STK_PARSER,                        /**< [TM.TMM.AT] Force stacking parser enable/disable*/
    CTC_GLOBAL_MAX_HECMP_MEM,                           /**< [TM] Cfg max member number for hecmp nexthop */
    CTC_GLOBAL_LB_HASH_GLOBAL_PROPERTY,                 /**< [TM.TMM.AT] LB-Hash global property,refer to ctc_lb_hash_global_property_t */
    CTC_GLOBAL_MAC_LIMIT_MODE,                          /**< [D2.TM.TMM.AT] Configure mac limit mode, value:uint32, 0:hardware mac limit mode, 1: software mac limit mode.*/
    CTC_GLOBAL_NPM_IM_COLOR_HW_EN,                      /**< [TMM] Enable NPM In-Band color by hardware, uint32*, not zero means enable, 0 menas disable */
    CTC_GLOBAL_MAX_IPV4_ICMP_PKT_SIZE,                  /**< [TM.TMM.AT] If not 0, means that ipv4 icmp packet length larger than this will be discard */
    CTC_GLOBAL_MAX_IPV6_ICMP_PKT_SIZE,                  /**< [TM.TMM.AT] If not 0, means that ipv6 icmp packet length larger than this will be discard */
    CTC_GLOBAL_MIN_TCP_HDR_SIZE,                        /**< [TM.TMM.AT] If not 0, first TCP fragments that have a TCP header smaller than this will be discard */
    CTC_GLOBAL_SCL_PAYLOAD_OFFSET_GRANU,                /**< [D2.TM] Configure Scl force_decap/snooping_parser payload offset granularity, refer to ctc_scl_payload_offset_granu_t */
    CTC_GLOBAL_ECO_EN,                                  /**< [TMM.AT] if set, means enable energy conservation mode, some functions will be disable, refer to ctc_global_eco_mode_t*/
    CTC_GLOBAL_VCHIP_INFO,                              /**< [AT] Virtual chip info, ref to ctc_global_vchip_info_t */
    CTC_GLOBAL_TRUNCATION_LEN_PROFILE,                  /**< [D2.TM.TMM.AT] Truncation len profile value: void* refer to ctc_truncation_len_t*/
    CTC_GLOBAL_MACDA_HIT_AGING_EN,                      /**< [TM.TMM.AT]  1: indicate mac da hit will update FDB entry aging status, 2: only for mc mac-da, 3: only for uc mac-da, 0:disable */
    CTC_GLOBAL_LOOP_MODE,                               /**< [TMM.AT] loop mode. 
                                                                TMM: 0: support 2 loop ports (dp0:1 dp1:1) 1: use 2 channel linkagg group to load banance 2: support 4 loop ports(dp0:2 dp1:2)
                                                                AT: 0: support pp num loop ports 1: use channel linkagg group 2: support 2*pp num loop ports*/
    CTC_GLOBAL_DECAPED_FORCE_IPMC,                      /**< [TM.TMM.AT] If set, the IPMC packets carried by tunnel will be forced to do IPMC lookup after decapsulation, value: uint32*, 0 or 1.*/
    CTC_GLOBAL_MCAST_LOGIC_REP_THRD,                    /**< [TMM.AT] Mcast do logic replicate if member count equal the threshold when mcast group and member have logic repicate ability*/
    CTC_GLOBAL_LOGIC_PORT_ISOLATE_EN,                   /**< [AT] logic port isolate enable, Egress PVLAN and port isoation not support*/
    CTC_GLOBAL_STATION_MOVE_MODE,                       /**< [AT] Station move mode: 0-normal mode and support priority 0~1;1-enhanced mode and support priority 0~15, Default is 0*/
    CTC_GLOBAL_TRUNCATION_MODE,                         /**< truncation mode refer to ctc_truncation_mode_t*/
    CTC_GLOBAL_TRUNCATION_LEN,                          /**< gloabl truncation length*/
    CTC_GLOBAL_CONTROL_MAX
};
typedef enum ctc_global_control_type_e ctc_global_control_type_t;

enum ctc_scl_payload_offset_granu_e
{
    CTC_SCL_PAYLOAD_OFFSET_GRANU_1,    /**< [D2.TM] Granularity is 1 byte*/
    CTC_SCL_PAYLOAD_OFFSET_GRANU_2,    /**< [D2.TM] Granularity is 2 byte*/
    CTC_SCL_PAYLOAD_OFFSET_GRANU_4,    /**< [D2.TM] Granularity is 4 byte*/
    CTC_SCL_PAYLOAD_OFFSET_GRANU_8,    /**< [D2.TM] Granularity is 8 byte*/
    CTC_SCL_PAYLOAD_OFFSET_GRANU_MAX
};
typedef enum ctc_scl_payload_offset_granu_e ctc_scl_payload_offset_granu_t;


#ifdef __cplusplus
}
#endif

#endif

